PLC RAM Storage Area in 2026: MRAM, Battery-Backed SRAM & IEC 61131-3
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Engineering Notes · PLC Memory · 2026 Update
By KOEED Engineering Desk · 2026-06-30 · 9 min read · Category: Engineering Notes
The RAM storage area of a PLC is no longer a single flat block of memory. In 2026 it is a hierarchy: DDR DRAM for the scan, MRAM or FRAM for retain, super-cap-backed SRAM for warm-restart, and industrial NAND for the program image. This refresh of our 2024 primer walks engineers through the modern memory model, the retention chemistries shipping on Allen-Bradley, Siemens, and Mitsubishi CPUs, and the IEC 61131-3 retention keywords that govern them.
AI Summary
Key Takeaways
- Modern PLC RAM is split into retain, non-retain, and persistent zones per IEC 61131-3, not a single flat block.
- Battery-backed SRAM is being replaced by MRAM and super-cap-backed FRAM on new ControlLogix, S7-1500, and iQ-R CPUs.
- Process image, retentive tags, and recipe data each get distinct memory classes — mixing them is the #1 commissioning bug.
- OPC UA Pub/Sub and MQTT publish retain memory into the cloud, requiring signed firmware and a documented patch cadence.
- KOEED stocks both legacy battery-backed modules and current MRAM-based CPUs for in-place repair and forward migration.
The 2026 PLC RAM landscape splits volatile program space from persistent data, with MRAM and super-cap-backed SRAM replacing coin cells on modern Allen-Bradley, Siemens, and Mitsubishi CPUs.
What changed since 2024
Three shifts matter for anyone maintaining a working PLC line in 2026:
- Retention chemistry upgrade. New Allen-Bradley 1756-L8x ControlLogix, Siemens S7-1500 / ET200, and Mitsubishi iQ-R CPUs ship with MRAM or FRAM retain backed by super-capacitors instead of a coin-cell battery. No scheduled battery swaps, no low-battery faults at commissioning.
-
IEC 61131-3 4th edition alignment. Retention is now expressed declaratively in code:
VAR RETAINfor warm-restart data,VAR PERSISTENTfor cold-restart (cycle-counted, recipes, audit trail). The runtime allocates memory for each class separately. - Process image size growth. 1756-L8x controllers can hold a 32 MB process image; S7-1500 CPUs address up to 6 MB of bit-mapped I/O. Older rule-of-thumb "RAM = 64 KB" no longer applies — but it does still apply to legacy Allen-Bradley SLC 500 and Siemens S7-300 modules still in service.
! Warning
If you hot-swap a ControlLogix 1756-L7x battery on a powered-off chassis, give the super-cap 30 s to back up retain before pulling the cell. On 1756-L8x / iQ-R / S7-1500 with MRAM, the cell is gone — losing external power for >72 h still keeps retain, but losing it while the controller is writing a recipe block can corrupt that single record.
The 2026 PLC RAM memory model
Forget "one RAM block." Modern runtimes partition the RAM storage area into classes, each with its own backup policy:
| Memory Class | Survives Power Loss? | Typical 2026 Backend | Example Use |
|---|---|---|---|
| Volatile work memory | No | DDR3L / LPDDR4 DRAM | Ladder execution, scan I/O |
| Retain data (warm restart) | Yes | MRAM / FRAM / super-cap SRAM | Counters, setpoints, state bits |
| Persistent data (cold restart) | Yes (cycles counted) | MRAM / industrial NAND | Recipes, audit trail, hours run |
| Program memory | Yes (flash-backed) | SLC NAND + firmware CRC | Ladder / ST / FBD code image |
| Process image (I/O) | No (refreshed each scan) | DRAM mapped to backplane | Live input / output bit mirrors |
Two takeaways from the table. First, "RAM" today is a hierarchy, not a single chip — DRAM for speed, MRAM/FRAM for retention, NAND for the program image. Second, retention policy is now declared per-tag, not enforced by a global jumper. The migration cost is in renaming, not in hardware.
Retention chemistries in the field
Across the nine KOEED brands, you'll meet three retention backends on the bench this year:
| Backend | How it holds data | Endurance | 2026 examples |
|---|---|---|---|
| Battery-backed SRAM (BBRAM) | BR2032 / ½AA lithium cell | Unlimited writes until cell | Allen-Bradley 1756-L7x, SLC 500 1747 |
| Super-cap-backed SRAM | 5–10 F super-cap, ~72 h hold | Unlimited writes | Schneider Modicon M580, Omron NJ/NX |
| MRAM (magnetoresistive) | Spin-torque, no cell, no cap | 1012 writes, byte-grammable | 1756-L8x, S7-1500 CPU 1518, Mitsubishi iQ-R R08CPU |
| FRAM (ferroelectric) | Polarisation state, non-volatile | 1014 writes | Panasonic FP7, Yaskawa MP3300 retain |
> Tip
When migrating from a battery-backed 1756-L7x to a 1756-L8x, the retain budget transfers 1:1 in bytes but the new controller expects a project-level "Remain I/O on STOP" attribute instead of the legacy BTR/BTW retain mask. Set this in the controller properties before going online or you will lose the first scan's setpoints.
IEC 61131-3 retention keywords
The third edition of IEC 61131-3 added VAR RETAIN; the fourth edition adds VAR PERSISTENT for cold-restart data. In practice:
- VAR RETAIN — setpoints, counters, last-good state. Restored on warm restart; cleared on cold restart or project download.
- VAR PERSISTENT — recipe batches, audit trail, lifetime counters. Restored across cold restart, downloads, and firmware updates if the project CRC matches.
- VAR (default) — work memory only; reinitialised every scan cycle.
Most modern runtimes enforce these classes at compile time. If you copy a 1990s Mitsubishi MELSEC-A ladder into a current GX Works project, the implicit D-register retain will be reclassified — and an unsuspecting engineer will see the recipe table clear itself on the first power cycle.
Process image vs. RAM — still confused in 2026
Two decades on, the most common field question is "why did my input bit toggle even though I never wrote to it?" The answer is the process image: a per-scan mirror of I/O mapped into the same DRAM address space the ladder reads from. It is part of the RAM storage area, but it is not retain memory, and writing to it has no effect on the physical module. The same trap exists on Omron CP1H, KEYENCE KV-8000, and Yaskawa MP2300 platforms.
What to do at the next maintenance window
- Inventory every CPU on the line. Note the battery date code for BBRAM modules; anything older than 5 years gets a cell swap before it leaks.
- For 1756-L8x / S7-1500 / iQ-R CPUs, run a project-level retain check and verify the CRC before firmware update.
- Replace used retain words with named symbolic tags — the runtime can compress them, but legacy fixed-address maps cannot.
- Back up the project + retain file via the OEM tool, not just the program. Studio 5000, TIA Portal, and GX Works3 each export a separate retain snapshot.
For cross-references on specific CPU modules and migration paths, browse the Allen-Bradley, Siemens, and Mitsubishi collection pages, or use the PLC Error Code Database to look up "retain lost" or "low battery" faults by part number. Need a working CPU with verified retain memory today? Send your BOM to Moritta@KOEED.COM and we will quote active and EOL stock side by side within 24 hours.
Need a verified-retain CPU or replacement battery module?
Send your BOM to Moritta@KOEED.COM. We stock legacy BBRAM modules, current MRAM CPUs, and battery accessories for Allen-Bradley, Siemens, Mitsubishi, and the other 7 brands — quote within 24 hours.
Send My BOM →Related on KOEED Blog
- Engineering Notes — weekly deep dives on retain, process image, and IEC 61131-3 keywords.
- Daily PLC News — vendor announcements and EOL alerts.
- PLC Error Code Database — Siemens / Mitsubishi / Omron fault lookup.
- CPUs and memories in PLC — sister primer on controller silicon.
- PLC scan cycle — how the runtime consumes the process image.
- Open PLC architecture in 2026 — how CODESYS / PLCnext runtimes manage retain.
KOEED Engineering Desk
Industrial automation editors at KOEED. We write about PLC memory, sourcing, cross-reference, and legacy system support. Reach the team at Moritta@KOEED.COM .
Frequently asked questions
What is the difference between RAM and retain memory in a PLC?
RAM is the controller's working memory — program code, scan-time data, and the process image. Retain memory is a reserved portion that survives power loss, backed by a battery, super-capacitor, or non-volatile MRAM / FRAM. Volatile RAM is wiped on every power cycle; retain memory is not.
Does my 2026 PLC still need a backup battery?
Probably not. New Allen-Bradley 1756-L8x, Siemens S7-1500, and Mitsubishi iQ-R CPUs use MRAM or FRAM with super-capacitor hold-up — no scheduled cell swap. Legacy L7x, SLC 500, S7-300, and MELSEC-Q CPUs still use a BR2032 or ½AA lithium cell that should be replaced every 3–5 years.
What happens if I lose retain memory during commissioning?
Setpoints revert to their initial values, counters reset to zero, and recipes clear. In safety-critical lines a retain loss is treated as a fault and the line will not start until the recipe is reloaded. Always export the retain snapshot via Studio 5000 / TIA Portal / GX Works3 before any download.
Can I mix VAR RETAIN and VAR PERSISTENT in the same program?
Yes. Use RETAIN for warm-restart state (setpoints, current step index) and PERSISTENT for cold-restart data (recipe batches, audit trail, lifetime counters). Mixing them is the recommended IEC 61131-3 fourth-edition pattern and is supported on every current runtime we stock.
How do I migrate retain data from an SLC 500 to a ControlLogix?
Map legacy integer file N7:N to symbolic INT[ ] tags with RETAIN attribute, legacy binary file B3:N to BOOL[ ] with RETAIN. The byte count transfers 1:1. Do not rely on the old file / element numbering — the symbolic rename is what makes the new project auditable.
Where does KOEED keep stock of verified-retain CPUs?
Active stock of 1756-L7x / L8x, S7-1500 / S7-300, and iQ-R / Q-Series CPUs ships from our Shenzhen + Hong Kong warehouses. Send your BOM to Moritta@KOEED.COM for a 24-hour quote with stock and lead time.