PLC CPU and Memory Architecture: 2026 Engineering Notes

Two years on from the 2024 introduction to PLC CPU and memory, the heart of a controller has changed quietly but firmly. Single-cycle bit-logic microcontrollers have given way to multicore ARM Cortex-A/M SoCs; battery-backed SRAM has been replaced by MRAM, FRAM, and DDR4 with ECC; and the IEC 61131-3 programming model now ships with classes, namespaces, and method inheritance. This 2026 Engineering Note refreshes the core architecture for engineers maintaining AB ControlLogix, Siemens SIMATIC S7, Mitsubishi MELSEC iQ-R, and Omron NJ/NX platforms in production today.

AI Summary

• Modern PLC CPUs are multicore ARM Cortex-A53/A55 SoCs with a dedicated Cortex-M4 real-time core and a security core, not single MCUs.
• Memory is tiered: non-volatile MRAM or FRAM for program and retain data, plus DDR4 with SEC-DED ECC for working memory. Battery-backed SRAM is going away.
• IEC 61131-3 4th edition (2025) extends POUs with classes, namespaces, interfaces, and method inheritance.
• Cybersecurity (IEC 62443-4-2 SL2) and OPC UA over TSN are now procurement-shaping requirements on new CPU modules.

In short, the 2026 PLC CPU is a multicore SoC with ECC-protected DDR and MRAM/FRAM non-volatile storage, scheduled by a real-time OS and hardened per IEC 62443-4-2.

By KOEED Engineering Desk · 2026-06-30 · 9 min read · Engineering Notes

1. The CPU — from bit-logic MCU to multicore SoC

The Central Processing Unit is still the brain of the PLC, but the silicon has changed. A 2000s-era SLC 500 processor ran a single 16-bit microcontroller at roughly 20 MHz with tightly coupled ROM and battery-backed RAM. The 2024 generation (Allen-Bradley 1756-L8x, Siemens CPU 1517) used a single ARM Cortex-A9 at 1 GHz with DDR3 and removable SD storage. The 2026 generation is now multicore: a typical mid-range CPU module combines one or two Cortex-A53/A55 application cores with a separate Cortex-M4 real-time core for the deterministic I/O scan, and a dedicated security core for secure boot and OPC UA authentication.

In practice this means three runtimes coexist on the same die: the IEC 61131-3 application runtime, the motion / NC runtime, and a real-time I/O scanner that runs independently of the application CPU. The application CPU can be reflashed or momentarily paused for a firmware update without dropping the fieldbus. For migration planning, this is the biggest shift since 2024 and it changes how you size a CPU for a project: you are no longer sizing bit-logic throughput, you are sizing application threads, motion axes, and security workload.

ALU, control unit, and register file — what stayed the same

The classical picture of an Arithmetic Logic Unit feeding a register file under a control unit still applies. What changed is the unit of work. A "scan" in 2026 is no longer a single sweep of ladder logic; it is a set of time-triggered tasks scheduled by a real-time operating system (typically a PREEMPT_RT-patched Linux or a vendor RTOS such as VxWorks, CODESYS Realtime, or 3S Smart OS). The PLCopen task model has matured into a four-quadrant scheduling grid: cyclic, event, freewheeling, and time-triggered (IEEE 1588 synchronized).

2. Memory tiering: MRAM, FRAM, and ECC DDR

Memory architecture has changed the most. The 2024 picture — battery-backed SRAM for retain data, NAND flash for program, optional DDR for working memory — has been replaced by a 2026 tiered design:

Tier	2024 typical	2026 typical	Why it changed
Non-volatile program	Battery-backed SRAM / NAND	MRAM (Everspin, 16–64 MB) or FRAM (Cypress, 8–32 MB)	No battery to fail, byte-level write, 10× endurance vs. flash
Working memory	DDR3 512 MB – 2 GB	DDR4 2–8 GB with SEC-DED ECC	Larger tag databases, OPC UA buffers, AI inference scratch
Removable recipe	SD card (FAT32)	Industrial SD / SMC with wear-leveling, signed firmware	IEC 62443-4-2 SL2 requires signed image
Boot / firmware	Mask ROM / NOR flash	Secure-boot NOR + TPM 2.0 module	Supply-chain integrity, signed firmware updates

3. Programming model: IEC 61131-3 4th edition OO

The IEC 61131-3 4th edition (published mid-2025) extends the POU model with classes, namespaces, interfaces, and method inheritance. Studio 5000 v36 already ships with method-on-tag, TIA Portal V19 exposes namespaces, and GX Works3 1.110 added interface inheritance for FBD blocks. The practical effect is that a "function block" is no longer a black box; it can be subclassed, and methods can be polymorphic. For brownfield code, this is opt-in — old ladder logic still scans.

4. What changed since 2024

The 2024 introduction to PLC CPU and memory framed the controller as "CPU + ROM + RAM." Three things have moved since then, and procurement specs have to follow:

Dimension	2024	2026
CPU core	Single ARM Cortex-A9, 1 GHz	2–4 cores: A53/A55 app + M4 RT + security
Non-volatile memory	Battery-backed SRAM + NAND	MRAM / FRAM, no battery
Working RAM	DDR3, 512 MB – 2 GB	DDR4 with ECC, 2–8 GB
Cybersecurity	Password + role	IEC 62443-4-2 SL2, signed firmware, TPM 2.0
Programming	IEC 61131-3 3rd ed., POUs only	IEC 61131-3 4th ed., classes + methods
Fieldbus	PROFINET / EtherNet/IP	+ OPC UA over TSN, SPE (Single Pair Ethernet)

5. Cross-reference: 2024 CPUs vs. 2026 successors

If you are mid-cycle on a refresh, the practical 2024-to-2026 CPU upgrade path is:

Brand	2024 CPU	2026 successor	Gain
Allen-Bradley	1756-L73 / L75	1756-L85EP	2× cores, ECC DDR4, OPC UA server on-board
Siemens	CPU 1515-2 PN	CPU 1518-4 PN/DP (G2)	Multicore, integrated TSN switch, OPC UA pub/sub
Mitsubishi	R08CPU	R16ENCPU	C/C++ runtime alongside IEC, CC-Link IE TSN
Omron	NJ501-1300	NX502-1400	SQL on-board, OPC UA pub/sub, OPC UA over TSN

6. Sourcing implications for 2026

The shift in CPU and memory architecture is also a shift in failure modes. Where the 2010-era engineer worried about lithium battery failure on a 1747 or FX2N, the 2026 engineer worries about MRAM wear, ECC single-bit error rates, and TPM 2.0 key provisioning. KOEED stocks the Allen-Bradley, Siemens, Mitsubishi, and Omron families alongside obsolete and EOL SKUs — for new builds, lead with the 2026 generation; for brownfield, KOEED's China Sourcing Company pipeline still sources 1747-ASB and 1746-BAS modules.

Related on KOEED Blog

• Browse the full Engineering Notes series
• Allen-Bradley ControlLogix modules — active and EOL stock
• Siemens S7-1500 / S7-300 modules — migration and spare parts
• PLC Error Code Database — Siemens / Mitsubishi / Omron fault codes
• PLC Hex to Float Converter — IEEE 754 debugging
• AI Diagnostic Tool — photograph a CPU nameplate for cross-reference
• Create a Quote — BOM-based multi-line RFQ form

Frequently Asked Questions

What is the CPU of a PLC in simple terms?

The CPU executes the user program, scans I/O, and handles communication. In 2026 most PLC CPUs are multicore ARM SoCs — typically one or two application cores plus a real-time core for the I/O scan.

What kind of memory does a PLC use today?

A 2026 PLC uses non-volatile MRAM or FRAM for program and retain data, plus DDR4 with ECC for working memory. Battery-backed SRAM is being phased out.

Why is ECC memory important in a PLC?

ECC detects and corrects single-bit RAM errors. For controllers running 24/7 with large tag databases and OPC UA buffers, ECC prevents silent data corruption from bit flips in long-running installations.

Has IEC 61131-3 changed recently?

Yes. The 4th edition (2025) added object-oriented extensions: classes, namespaces, interfaces, and method inheritance. Vendors like Rockwell, Siemens, and Mitsubishi are gradually rolling the new features into their tools.

Where can I source an EOL PLC CPU?

Independent multi-brand distributors such as KOEED keep both active and EOL stock. Send the BOM to Moritta@KOEED.COM and we will respond with availability and a quote within 24 hours.