A PLC host in 2026: still three components, but the silicon has changed

Detail

The classic three-block model (CPU + I/O + memory) is still the right way to teach and troubleshoot a PLC host in 2026.

Modern CPU modules now ship as multicore SoC designs: a real-time core for the scan task, a separate security/crypto core, and an optional motion or C/C++ runtime core on the same die.

I/O has split into two parallel tiers: classic backplane I/O (digital, analog, specialty) and IO-Link / IO-Link Wireless master modules for low-cost sensor-level integration.

Retain memory in 2026 is split across three technologies: NAND flash for project storage, FRAM for high-endurance retain tags, and DDR4 with ECC for working memory.

In 2024 we wrote that the CPU is the brain of the PLC. That is still true in 2026, but the brain is no longer a single processor. The current generation of high-end PLC CPUs , Siemens SIMATIC S7-1500 G2, Allen-Bradley ControlLogix 5580 (1756-L8x), Mitsubishi MELSEC iQ-R (RnCPU), and Omron NX/NJ-series NX102 / NX502 , all use a multicore system-on-chip design.

, runs the deterministic scan task, PID loops, and motion planning. This is the only core with direct access to the backplane I/O.

, handles TLS 1.3 for OPC UA, signed firmware verification, and IEC 62443-4-2 secure boot. On ControlLogix 5580 this is a separate ARM Cortex-A core; on S7-1500 G2 it is integrated into the SoC but isolated at the hardware level.