PLC RAM Storage Area in 2026: MRAM, Battery-Backed SRAM & IEC 61131-3

Detail

of a PLC is no longer a single flat block of memory. In 2026 it is a hierarchy: DDR DRAM for the scan, MRAM or FRAM for retain, super-cap-backed SRAM for warm-restart, and industrial NAND for the program image. This refresh of our 2024 primer walks engineers through the modern memory model, the retention chemistries shipping on

Modern PLC RAM is split into retain, non-retain, and persistent zones per IEC 61131-3, not a single flat block.

Battery-backed SRAM is being replaced by MRAM and super-cap-backed FRAM on new ControlLogix, S7-1500, and iQ-R CPUs.

Process image, retentive tags, and recipe data each get distinct memory classes , mixing them is the #1 commissioning bug.

OPC UA Pub/Sub and MQTT publish retain memory into the cloud, requiring signed firmware and a documented patch cadence.

KOEED stocks both legacy battery-backed modules and current MRAM-based CPUs for in-place repair and forward migration.

The 2026 PLC RAM landscape splits volatile program space from persistent data, with MRAM and super-cap-backed SRAM replacing coin cells on modern Allen-Bradley, Siemens, and Mitsubishi CPUs.

CPUs ship with MRAM or FRAM retain backed by super-capacitors instead of a coin-cell battery. No scheduled battery swaps, no low-battery faults at commissioning.